- Applications are invited for Junior Research Fellow (JRF) and Senior Project Associate (SPA) roles under the R&D project titled ‘Low overhead MBIST for embedded memories in SoCs’ sanctioned by ISRO under the RESPOND Programme.
- The positions are co-terminous with the project duration and may be extended based on performance.
- Location: Indian Institute of Technology Jammu, Jammu & Kashmir.
IIT
Active Listing
🎓 B.Tech
🎓 B.E.
🎓 M.Sc.
🎓 M.Tech
🎓 Ph.D.
Junior Research Fellow (JRF) and Senior Project Associate (SPA) in VLSI Testing
Indian Institute of Technology Jammu
Total Vacancies
2
Job Location
Indian Institute of Technology Jammu, Jammu & Kashmir
Apply Deadline
05 Oct 2026
📋 Recruitment Overview
| Organization | Indian Institute of Technology Jammu (IIT Jammu) |
| Job Category | Technical |
| Eligibility Qualification | B.Tech (btech), B.E. (be), M.Sc. (msc), M.Tech (mtech), Ph.D. (phd) |
| Number of Vacancies | 2 Posts |
| Salary / Pay Scale | ₹37,000 - ₹42,000 Per Month |
| Age Limits | Maximum 40 Years |
| Gender Eligibility | both |
| Experience Required | • JRF: No minimum experience required; preference given to candidates with experience in Digital VLSI Design and Test. • SPA: 4 years of experience in R&D for candidates with M.E./M.Tech. or equivalent. |
| Application Fee | No application fee mentioned in the notification. |
📄 Details & Description
🎓 Eligibility Criteria
• Junior Research Fellow (JRF): ['- Qualification: M.E./M.Tech./MS(R) or equivalent degree in CSE/ECE/EE/Microelectronics/VLSI Design and allied subjects with 60% marks (5% relaxation for ST/SC/PH candidates). Students awaiting results may apply.', '- OR: B.E./B.Tech./M.Sc. in CSE/ECE/EE/Electronics/Microelectronics/VLSI Design/Embedded Systems with 60% marks (5% relaxation for ST/SC/PH candidates). Students awaiting results may apply.', '- Eligibility Test: Qualified in CSIR-UGC NET (Lectureship/Assistant Professorship), GATE, or other national-level exams (e.g., DST, DBT, DAE, DRDO, MoE, ICAR, ICMR, IIT, IISc, IISER, NISER).', '- Desirable: Experience in Digital VLSI Design, Memory Testing, FPGA Implementation, HDLs (VHDL/Verilog/System Verilog), and EDA tools (Cadence, Mentor Graphics, Synopsys).']
• Senior Project Associate (SPA): ['- Qualification: Doctoral Degree in Science/Engineering/Technology in CSE/ECE/EE/Electronics/Microelectronics/VLSI Design/Embedded Systems and allied disciplines from a recognized university.', '- OR: M.E./M.Tech. or equivalent degree in CSE/ECE/EE/Microelectronics/VLSI Design and allied disciplines OR B.E./B.Tech. in the same fields with 60% marks or equivalent CGPA, plus 4 years of experience in R&D in academic/industrial institutions or ST organizations.', '- Desirable: Sound knowledge in Design-for-Test (DfT) Architectures, Memory Test (MBIST), MBIST Algorithms (MARCH and Non-MARCH), SoC-level DFT integration, FPGA/ASIC prototyping, HDLs (VHDL/Verilog/System Verilog), HLLs (Python, C++), and EDA tools (Cadence, Synopsys).']
• Senior Project Associate (SPA): ['- Qualification: Doctoral Degree in Science/Engineering/Technology in CSE/ECE/EE/Electronics/Microelectronics/VLSI Design/Embedded Systems and allied disciplines from a recognized university.', '- OR: M.E./M.Tech. or equivalent degree in CSE/ECE/EE/Microelectronics/VLSI Design and allied disciplines OR B.E./B.Tech. in the same fields with 60% marks or equivalent CGPA, plus 4 years of experience in R&D in academic/industrial institutions or ST organizations.', '- Desirable: Sound knowledge in Design-for-Test (DfT) Architectures, Memory Test (MBIST), MBIST Algorithms (MARCH and Non-MARCH), SoC-level DFT integration, FPGA/ASIC prototyping, HDLs (VHDL/Verilog/System Verilog), HLLs (Python, C++), and EDA tools (Cadence, Synopsys).']
⚙️ Selection Process
- Shortlisting based on merit and project requirements.
- Interview for shortlisted candidates (online/offline).
- Final selection based on interview performance.
- Interview for shortlisted candidates (online/offline).
- Final selection based on interview performance.
🏷️ Category Eligibility & Reservations
General, OBC, SC, ST, PwD
📂 Required Documents
- Duly filled application form.
- Scanned copies of academic certificates (10th, 12th, graduation, post-graduation, etc.).
- Proof of eligibility test qualification (e.g., GATE/NET scorecard).
- Experience certificates (if applicable).
- Relieving certificate (if currently employed).
- Valid email ID and phone number for interview communication.
- Scanned copies of academic certificates (10th, 12th, graduation, post-graduation, etc.).
- Proof of eligibility test qualification (e.g., GATE/NET scorecard).
- Experience certificates (if applicable).
- Relieving certificate (if currently employed).
- Valid email ID and phone number for interview communication.
💳 Application Fee Details
No application fee mentioned in the notification.
❓ Frequently Asked Questions
Q.
How many vacancies are available for JRF and SPA roles at IIT Jammu?
There are 1 vacancy each for Junior Research Fellow (JRF) and Senior Project Associate (SPA) under the project ‘Low overhead MBIST for embedded memories in SoCs’.
Q.
What is the last date to apply for these positions?
The last date to apply is 5 October 2026.
Q.
What is the maximum age limit for the Senior Project Associate (SPA) position?
The maximum age limit for SPA is 40 years, with relaxations for SC/ST/PwD (5 years) and OBC-NCL (3 years) as per Government of India guidelines.
Q.
Is there an application fee for these positions?
No, the notification does not mention any application fee for these roles.
Q.
What qualifications are required for the JRF position?
For JRF, candidates must have either a M.E./M.Tech./MS(R) or B.E./B.Tech./M.Sc. in CSE/ECE/EE/Microelectronics/VLSI Design with 60% marks (5% relaxation for ST/SC/PH) OR qualify in CSIR-UGC NET/GATE or other national-level exams.